In general, it necessarily requires short channel length, reduction of contact depths of a source and a drain, and reduction of effective gate oxide thickness to attain high power performance, high efficiency integration, and high speed operation characteristics. The development of vertical transistors has increased with the downsizing of the semiconductor devices. Examples of known vertical transistors are disclosed in U.S. Pat. Nos. 6,597,037, 6,486,027 6,153,468, 6,124,729, and 5,991,225.
Device performance increases should be attained by means of increase of driving current and reduction of leakage current. However, in a conventional process, there are some problems associated with fabricating a fine silicon device having such high performance. For example, although it is necessary to use new patterning techniques, such as electron beam or X-ray exposure-based techniques, of forming ultra fine patterns to fabricate nano-size channels as a conventional planar structure, because such techniques are not established until today, it is not currently possible to mass produce ultra fine silicon devices requiring ultra fine patterns.